mirror of
https://github.com/go-gitea/gitea
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Vendor Update Go Libs (#13166)
* update github.com/alecthomas/chroma v0.8.0 -> v0.8.1 * github.com/blevesearch/bleve v1.0.10 -> v1.0.12 * editorconfig-core-go v2.1.1 -> v2.3.7 * github.com/gliderlabs/ssh v0.2.2 -> v0.3.1 * migrate editorconfig.ParseBytes to Parse * github.com/shurcooL/vfsgen to 0d455de96546 * github.com/go-git/go-git/v5 v5.1.0 -> v5.2.0 * github.com/google/uuid v1.1.1 -> v1.1.2 * github.com/huandu/xstrings v1.3.0 -> v1.3.2 * github.com/klauspost/compress v1.10.11 -> v1.11.1 * github.com/markbates/goth v1.61.2 -> v1.65.0 * github.com/mattn/go-sqlite3 v1.14.0 -> v1.14.4 * github.com/mholt/archiver v3.3.0 -> v3.3.2 * github.com/microcosm-cc/bluemonday 4f7140c49acb -> v1.0.4 * github.com/minio/minio-go v7.0.4 -> v7.0.5 * github.com/olivere/elastic v7.0.9 -> v7.0.20 * github.com/urfave/cli v1.20.0 -> v1.22.4 * github.com/prometheus/client_golang v1.1.0 -> v1.8.0 * github.com/xanzy/go-gitlab v0.37.0 -> v0.38.1 * mvdan.cc/xurls v2.1.0 -> v2.2.0 Co-authored-by: Lauris BH <lauris@nix.lv>
This commit is contained in:
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GitHub
60
vendor/golang.org/x/sys/cpu/cpu.go
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60
vendor/golang.org/x/sys/cpu/cpu.go
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@@ -29,26 +29,46 @@ type CacheLinePad struct{ _ [cacheLineSize]byte }
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// and HasAVX2 are only set if the OS supports XMM and YMM
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// registers in addition to the CPUID feature bit being set.
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var X86 struct {
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasRDRAND bool // RDRAND instruction (on-chip random number generator)
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HasRDSEED bool // RDSEED instruction (on-chip random number generator)
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasAVX512 bool // Advanced vector extension 512
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HasAVX512F bool // Advanced vector extension 512 Foundation Instructions
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HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions
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HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions
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HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions Instructions
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HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions
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HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions
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HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions
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HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add
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HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions
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HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision
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HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision
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HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions
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HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations
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HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions
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HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions
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HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions
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HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2
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HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms
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HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasRDRAND bool // RDRAND instruction (on-chip random number generator)
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HasRDSEED bool // RDSEED instruction (on-chip random number generator)
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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}
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// ARM64 contains the supported CPU features of the
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2
vendor/golang.org/x/sys/cpu/cpu_arm64.go
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2
vendor/golang.org/x/sys/cpu/cpu_arm64.go
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@@ -39,7 +39,7 @@ func initOptions() {
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func archInit() {
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switch runtime.GOOS {
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case "android", "darwin", "netbsd":
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case "android", "darwin", "ios", "netbsd":
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// Android and iOS don't seem to allow reading these registers.
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//
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// NetBSD:
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51
vendor/golang.org/x/sys/cpu/cpu_x86.go
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51
vendor/golang.org/x/sys/cpu/cpu_x86.go
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@@ -16,6 +16,26 @@ func initOptions() {
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{Name: "aes", Feature: &X86.HasAES},
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{Name: "avx", Feature: &X86.HasAVX},
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{Name: "avx2", Feature: &X86.HasAVX2},
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{Name: "avx512", Feature: &X86.HasAVX512},
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{Name: "avx512f", Feature: &X86.HasAVX512F},
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{Name: "avx512cd", Feature: &X86.HasAVX512CD},
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{Name: "avx512er", Feature: &X86.HasAVX512ER},
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{Name: "avx512pf", Feature: &X86.HasAVX512PF},
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{Name: "avx512vl", Feature: &X86.HasAVX512VL},
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{Name: "avx512bw", Feature: &X86.HasAVX512BW},
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{Name: "avx512dq", Feature: &X86.HasAVX512DQ},
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{Name: "avx512ifma", Feature: &X86.HasAVX512IFMA},
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{Name: "avx512vbmi", Feature: &X86.HasAVX512VBMI},
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{Name: "avx512vnniw", Feature: &X86.HasAVX5124VNNIW},
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{Name: "avx5124fmaps", Feature: &X86.HasAVX5124FMAPS},
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{Name: "avx512vpopcntdq", Feature: &X86.HasAVX512VPOPCNTDQ},
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{Name: "avx512vpclmulqdq", Feature: &X86.HasAVX512VPCLMULQDQ},
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{Name: "avx512vnni", Feature: &X86.HasAVX512VNNI},
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{Name: "avx512gfni", Feature: &X86.HasAVX512GFNI},
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{Name: "avx512vaes", Feature: &X86.HasAVX512VAES},
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{Name: "avx512vbmi2", Feature: &X86.HasAVX512VBMI2},
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{Name: "avx512bitalg", Feature: &X86.HasAVX512BITALG},
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{Name: "avx512bf16", Feature: &X86.HasAVX512BF16},
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{Name: "bmi1", Feature: &X86.HasBMI1},
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{Name: "bmi2", Feature: &X86.HasBMI2},
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{Name: "erms", Feature: &X86.HasERMS},
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@@ -59,12 +79,15 @@ func archInit() {
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X86.HasOSXSAVE = isSet(27, ecx1)
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X86.HasRDRAND = isSet(30, ecx1)
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osSupportsAVX := false
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var osSupportsAVX, osSupportsAVX512 bool
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// For XGETBV, OSXSAVE bit is required and sufficient.
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if X86.HasOSXSAVE {
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eax, _ := xgetbv()
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// Check if XMM and YMM registers have OS support.
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osSupportsAVX = isSet(1, eax) && isSet(2, eax)
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// Check if OPMASK and ZMM registers have OS support.
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osSupportsAVX512 = osSupportsAVX && isSet(5, eax) && isSet(6, eax) && isSet(7, eax)
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}
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X86.HasAVX = isSet(28, ecx1) && osSupportsAVX
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@@ -73,7 +96,7 @@ func archInit() {
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return
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}
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_, ebx7, _, _ := cpuid(7, 0)
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_, ebx7, ecx7, edx7 := cpuid(7, 0)
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X86.HasBMI1 = isSet(3, ebx7)
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X86.HasAVX2 = isSet(5, ebx7) && osSupportsAVX
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X86.HasBMI2 = isSet(8, ebx7)
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@@ -81,6 +104,30 @@ func archInit() {
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X86.HasRDSEED = isSet(18, ebx7)
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X86.HasADX = isSet(19, ebx7)
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X86.HasAVX512 = isSet(16, ebx7) && osSupportsAVX512 // Because avx-512 foundation is the core required extension
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if X86.HasAVX512 {
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X86.HasAVX512F = true
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X86.HasAVX512CD = isSet(28, ebx7)
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X86.HasAVX512ER = isSet(27, ebx7)
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X86.HasAVX512PF = isSet(26, ebx7)
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X86.HasAVX512VL = isSet(31, ebx7)
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X86.HasAVX512BW = isSet(30, ebx7)
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X86.HasAVX512DQ = isSet(17, ebx7)
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X86.HasAVX512IFMA = isSet(21, ebx7)
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X86.HasAVX512VBMI = isSet(1, ecx7)
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X86.HasAVX5124VNNIW = isSet(2, edx7)
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X86.HasAVX5124FMAPS = isSet(3, edx7)
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X86.HasAVX512VPOPCNTDQ = isSet(14, ecx7)
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X86.HasAVX512VPCLMULQDQ = isSet(10, ecx7)
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X86.HasAVX512VNNI = isSet(11, ecx7)
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X86.HasAVX512GFNI = isSet(8, ecx7)
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X86.HasAVX512VAES = isSet(9, ecx7)
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X86.HasAVX512VBMI2 = isSet(6, ecx7)
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X86.HasAVX512BITALG = isSet(12, ecx7)
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eax71, _, _, _ := cpuid(7, 1)
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X86.HasAVX512BF16 = isSet(5, eax71)
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}
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}
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func isSet(bitpos uint, value uint32) bool {
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